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MC10EP51DT データシート(PDF) 1 Page - ON Semiconductor

部品番号 MC10EP51DT
部品情報  3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 6
1
Publication Order Number:
MC10EP51/D
MC10EP51, MC100EP51
3.3V / 5VECL D Flip−Flop
with Reset and Differential
Clock
Description
The MC10/100EP51 is a differential clock D flip−flop with reset.
The device is functionally equivalent to the EL51 and LVEL51
devices.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip−flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EP51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to VEE and the CLK input will be biased at VCC/2.
The 100 Series contains temperature compensation.
Features
350 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
H
= MC10
K
= MC100
5S
= MC10
3N = MC100
M
= Date Code
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
ALYWG
G
HP51
ALYWG
G
KP51
1
8
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
DFN8
MN SUFFIX
CASE 506AA
14
14
(Note: Microdot may be in either location)
HEP51
ALYW
G
1
8
KEP51
ALYW
G
1
8


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