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MC10EPT20DR2G データシート(PDF) 1 Page - ON Semiconductor |
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MC10EPT20DR2G データシート(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 9 1 Publication Order Number: MC10EPT20/D MC10EPT20, MC100EPT20 3.3VLVTTL/LVCMOS to Differential LVPECL Translator The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the EPT20 makes it ideal for those applications where space, performance, and low power are at a premium. The 100 Series contains temperature compensation. Features • 390 ps Typical Propagation Delay • Maximum Input Clock Frequency > 1 GHz Typical • Operating Range VCC = 3.0 V to 3.6 V with GND = 0 V • PNP TTL Input for Minimal Loading • Q Output will Default HIGH with Input Open • Pb−Free Packages are Available A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package H = MC10 K = MC100 5W = MC10 3Q = MC100 M = Date Code MARKING DIAGRAMS* ALYWG G HA20 ALYWG G KA20 SO−8 D SUFFIX CASE 751 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 1 8 *For additional marking information, refer to Application Note AND8002/D. 1 8 HPT20 ALYW G 1 8 KPT20 ALYW G 1 8 http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION DFN8 MN SUFFIX CASE 506AA 14 14 (Note: Microdot may be in either location) |
同様の部品番号 - MC10EPT20DR2G |
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同様の説明 - MC10EPT20DR2G |
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