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MC26LS30DG データシート(PDF) 6 Page - ON Semiconductor |
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MC26LS30DG データシート(HTML) 6 Page - ON Semiconductor |
6 / 14 page MC26LS30 http://onsemi.com 6 Figure 4. Differential Mode Enable Timing NOTES: 1. S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns. 2. Above tests conducted by monitoring output current levels. Figure 5. Single−Ended Mode Rise/Fall Time and Data Propagation Delay NOTES: 1. S.G. set to: f p 100 kHz; duty cycle = 50%; tr, tf, p10 ns. 2. tSK4 = tPDH−tPDL for each driver. 3. tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package. 4. tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package. VEE tPZH tPZL tPLZ tPHZ 1.5 V Output Current (Vin = Lo) 0.1 VSS/RL 0.1 VSS/RL VSS/RL VSS/RL 0.5 VSS/RL 0.5 VSS/RL RL 0 or 3.0 V En VSS 500 pF 450 Ω S.G. VCC 450 CC +3.0 V 1.5 V 0 V Vin VCC Vin +2.5 V S.G. 500 pF VO (Vin = Hi) Vin 1.5 V Vout 10% 50% 90% tr 1.5 V 90% 0 V 10% Vin 50% tf tPDL tPDH |
同様の部品番号 - MC26LS30DG |
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同様の説明 - MC26LS30DG |
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