© 2004 Fairchild Semiconductor Corporation

DS500741

www.fairchildsemi.com

May 2002

Revised November 2004

74ALVCF322835

Low Voltage 36-Bit Universal Bus Driver

with 3.6V Tolerant Outputs

and 26

Ω Series Resistors in Outputs

General Description

The 74ALVCF322835 low voltage 36-bit universal bus

driver combines D-type latches and D-type flip-flops to

allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

a Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

The 74ALVCF322835 is designed with 26

Ω series resistors

in the outputs. This design reduces noise in applications

such as memory address drivers, clock drivers, and bus

transceivers/transmitters.

The 74ALVCF322835 is designed for low voltage (1.65V to

The 74ALVCF322835 is fabricated with an advanced

CMOS technology to achieve high speed operation while

maintaining low CMOS power dissipation.

Features

s Compatible with PC133 DIMM module specifications

s 3.6V tolerant outputs

s 26

Ω series resistors in outputs

s Power-down high impedance outputs

s Latchup conforms to JEDEC JED78

s ESD performance:

Human body model

> 2000V

Machine model

>200V

Ordering Code:

Note 1: Ordering Code “G” indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package

Number

Package Description

74ALVCF322835G

(Note 1)(Note 2)

BGA114A

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide