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MC74VHC08MELG データシート(PDF) 1 Page - ON Semiconductor

部品番号 MC74VHC08MELG
部品情報  Quad 2?묲nput AND Gate
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74VHC08MELG データシート(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 6
1
Publication Order Number:
MC74VHC08/D
MC74VHC08
Quad 2−Input AND Gate
The MC74VHC08 is an advanced high speed CMOS 2−input AND
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
Pb−Free Packages are Available*
3
Y1
1
A1
Figure 1. Logic Diagram
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
Figure 2. Pinout: 14−Lead Packages
13
14
12
11
10
9
8
2
1
34567
VCC
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
GND
(Top View)
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
SOIC−14
D SUFFIX
CASE 751A
TSSOP
DT SUFFIX
CASE 948G
SOEIAJ−14
M SUFFIX
CASE 965
http://onsemi.com
(Note: Microdot may be in either location)
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
1
14
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
L
L
L
H
Y
VHC
08
ALYW
G
G
1
14
1
14
74VHC08
ALYWG
VHC08G
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or
G = Pb−Free Package


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