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MC100EL39DWG データシート(PDF) 1 Page - ON Semiconductor

部品番号 MC100EL39DWG
部品情報  5V ECL 첨2/4, 첨4/6 Clock Generation Chip
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EL39DWG データシート(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 6
1
Publication Order Number:
MC100EL39/D
MC100EL39
5VECL ÷2/4, ÷4/6 Clock
Generation Chip
The MC100EL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple EL39s, the Master Reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EL39, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and
the ÷4/6 outputs of a single device.
Features
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with
VEE = −4.2 V to −5.7 V
Internal Input Pulldown Resistors on EN, MR, CLK(s), and
DIVSEL(s)
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
Transistor Count = 419 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= Pb−Free Package
SO−20 WB
DW SUFFIX
CASE 751D
20
1
100EL39
AWLYYWWG


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