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TPL9202PWP データシート(PDF) 9 Page - Texas Instruments |
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TPL9202PWP データシート(HTML) 9 Page - Texas Instruments |
9 / 17 page www.ti.com Timing Requirements Reset Delay (R DELAY) TPL9202 8-CHANNEL RELAY DRIVER WITH INTEGRATED 5-V LDO AND BROWN-OUT DETECTION SLIS124B – JUNE 2006 – REVISED NOVEMBER 2006 T A = –40°C to 125°C, VIN = 7 V to 18 V (unless otherwise stated) PARAMETER MIN TYP MAX UNIT fSPI SPI frequency 4 kHz T1 Delay time, NCS falling edge to SCLK rising edge 10 ns T2 Delay time, NCS falling edge to SCLK falling edge 80 ns T3 Pulse duration, SCLK high 60 ns T4 Pulse duration, SCLK low 60 ns T5 Delay time, last SCLK falling edge to NCS rising edge 80 ns T6 Setup time, MOSI valid before SCLK edge 10 ns T7 Hold time, MOSI valid after SCLK edge 10 ns T8 Time between two words for transmitting 170 ns The RDELAY output provides a constant current source to charge an external capacitor to approximately 6.5 V. The external capacitor is selected to provide a delay time, based on the current equation for a capacitor, I = C( ∆v/∆t) and a 28-µA typical output current. Therefore, the user should select a 47-nF capacitor to provide a 6-ms delay at 3.55 V. I = C( ∆v/∆t) 28 µA = C × (3.55 V/6 ms) C = 47 nF 9 Submit Documentation Feedback |
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同様の説明 - TPL9202PWP |
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