CAT25040LI-GT3 datasheet(5/18 Pages) CATALYST

部品番号	CAT25040LI-GT3

部品情報	1K/2K/4K SPI Serial CMOS EEPROM

Download	18 Pages

Scroll/Zoom	100%

メーカー	CATALYST [Catalyst Semiconductor]

ホームページ	http://www.catalyst-semiconductor.com

Logo

5 / 18 page

5

CAT25010, CAT25020, CAT25040

Doc. No. 1006, Rev. S

Characteristics subject to change without notice

Status Register Bits

Array Address

Protection

BP1

BP0

Protected

0

None

No Protection

0

1

CAT25010: 60-7F

Quarter Array Protection

CAT25020: C0-FF

CAT25040: 180-1FF

1

0

CAT25010: 40-7F

Half Array Protection

CAT25020: 80-FF

CAT25040: 100-1FF

1

CAT25010: 00-7F

Full Array Protection

CAT25020: 00-FF

CAT25040: 000-1FF

BLOCK PROTECTION BITS

76543210

1111

BP1

BP0

WEL

RDY

STATUS REGISTER

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to synchronize

the communication between the microcontroller and the

CAT25010/20/40. Opcodes, byte addresses, or data

present on the SI pin are latched on the rising edge of the

SCK. Data on the SO pin is updated on the falling edge

of the SCK for SPI modes (0,0 & 1,1) .

CS

CS: Chip Select

CS is the Chip select pin. CS low enables the CAT25010/

20/40 and

CS high disables the CAT25010/20/40. CS

high takes the SO output pin to high impedance and

forces the devices into a Standby Mode (unless an

internal write operation is underway). A high to low

transition on

CS is required prior to any sequence being

initiated. A low to high transition on

CS after a valid write

sequence is what initiates an internal write cycle.

WP

WP: Write Protect

WP is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high.

When

WP is tied low all write operations are inhibited.

WP held low while CS is low will interrupt a write to the

CAT25010/20/40. If the internal write cycle has already

been initiated,

WP going low will have no effect on any

write operation. Figure 10 illustrates the

WP timing

sequence during a write operation.

HOLD

HOLD: Hold

The

HOLD pin is used to pause transmission to the

CAT25010/20/40 while in the middle of a serial sequence

without having to re-transmit entire sequence at a later

time. To pause,

HOLD must be brought low while SCK

is low. The SO pin is in a high impedance state during

the time the part is paused, and transitions on the SI pins

will be ignored. To resume communication,

HOLD is

brought high, while SCK is low. (

HOLD should be held

high any time this function is not being used.)

HOLD may

be tied high directly to VCC or tied to VCC through a

resistor. Figure 9 illustrates hold timing sequence.

同様の部品番号 - CAT25040LI-GT3

メーカー	部品番号	データシート	部品情報
Catalyst Semiconductor	CAT25040LI-GT3	236Kb / 17P	1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM
ON Semiconductor	CAT25040LI-GT3	185Kb / 15P	1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM February, 2010 ??Rev. 21

More results

同様の説明 - CAT25040LI-GT3

メーカー	部品番号	データシート	部品情報
Catalyst Semiconductor	CAT25C01	374Kb / 15P	1K/2K/4K SPI Serial CMOS EEPROM
	CAT25010	73Kb / 11P	1K/2K/4K SPI Serial CMOS EEPROM
	CAT25C11	79Kb / 12P	1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
	CAT25C03	305Kb / 12P	1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
	CAT64LC10	300Kb / 12P	1K/2K/4K-Bit SPI Serial EEPROM
Asahi Kasei Microsystem...	AK93C45B	178Kb / 14P	1K / 2K / 4K / 8Kbit Serial CMOS EEPROM
	AK93C45B	166Kb / 14P	1K / 2K / 4K / 8KBIT SERIAL CMOS EEPROM
	AK93C45A	129Kb / 14P	1K / 2K / 4K / 8Kbit Serial CMOS EEPROM
Microchip Technology	85C72	107Kb / 8P	1K/2K/4K 5.0V CMOS Serial EEPROM 1995
Catalyst Semiconductor	CAT25C01	59Kb / 10P	1K/2K/4K/8K/16K SPI Serial CMOS E2PROM