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CAT24C208WIT3 データシート(PDF) 4 Page - Catalyst Semiconductor

部品番号 CAT24C208WIT3
部品情報  8-Kb Dual Port Serial EEPROM
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メーカー  CATALYST [Catalyst Semiconductor]
ホームページ  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT24C208WIT3 データシート(HTML) 4 Page - Catalyst Semiconductor

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CAT24C208
4
Doc. No. 1044, Rev. F
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does
not respond to its slave address.
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CI/O(1)
Input/Output Capacitance (Either DSP or DDC SDA)
VI/O = 0V
8
pF
CIN(1)
Input Capacitance (EDID, Either DSP or DDC SCL)
VIN = 0V
6
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
VCC = 2.5V to 5.5V, unless otherwise specified.
Read & Write Cycle Limits
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Power-Up Timing(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
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Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms


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