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CAT24C256WIT3 データシート(PDF) 4 Page - Catalyst Semiconductor |
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CAT24C256WIT3 データシート(HTML) 4 Page - Catalyst Semiconductor |
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4 / 14 page  CAT24C256 4 Doc. No. 04, Rev. D © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice PIn DESCRIPTIOn SCl: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device ad- dress. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write op- erations, when pulled HIGH. This pin has an on-chip pull-down resistor. funCTIOnAl DESCRIPTIOn The CAT24C256 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a devicereceivingdataasareceiver.Dataflowiscontrolled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C256 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device ad- dress inputs A0, A, and A2. I2C buS PROTOCOl The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2- wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure ). START TheSTARTconditionprecedesallcommands.Itconsists of a HIGH to LOW transition on SDA while SCL is HIGH. TheSTARTactsasa‘wake-up’calltoallreceivers.Absent a START, a Slave will not respond to commands. STOP TheSTOPconditioncompletesallcommands.Itconsists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when follow- ing a Write command) or sends the Slave into standby mode (when following a Read command). Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 00, for normal Read/Write opera- tions (Figure 2). The next 3 bits, A2, A and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 4. |
同様の部品番号 - CAT24C256WIT3 |
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同様の説明 - CAT24C256WIT3 |
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