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MC100EPT22DR2 データシート(PDF) 2 Page - ON Semiconductor |
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MC100EPT22DR2 データシート(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC100EPT22 http://onsemi.com 2 1 2 3 45 6 7 8 D0 GND VCC Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Q0 D1 Q1 Q1 Q0 LVPECL LVTTL Table 1. PIN DESCRIPTION PIN Q0, Q1, Q0, Q1 D0, D1 LVTTL Inputs FUNCTION LVPECL Differential Outputs VCC Positive Supply GND Ground EP Exposed pad must be con- nected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg SOIC−8 TSSOP−8 DFN8 Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 164 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
同様の部品番号 - MC100EPT22DR2 |
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同様の説明 - MC100EPT22DR2 |
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