データシートサーチシステム |
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CAT24WC08WITE13F データシート(PDF) 7 Page - Catalyst Semiconductor |
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CAT24WC08WITE13F データシート(HTML) 7 Page - Catalyst Semiconductor |
7 / 14 page CAT24WC01/02/04/08/16 7 Doc. No. 1022, Rev. N © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 24WCXX F09 Figure 7. Page Write Timing 5020 FHD F08 Figure 6. Byte Write Timing * P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16 * = Don't care for CAT24WC01 BUS ACTIVITY: MASTER SDA LINE DATA n+P BYTE ADDRESS (n) A C K A C K DATA n A C K S T O P S A C K DATA n+1 A C K S T A R T P SLAVE ADDRESS NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 * WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT24WC01/ 02/04/08/16 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ OPERATIONS The READ operation for the CAT24WC01/02/04/08/16 is initiated in the same manner as the write operation with the one exception that the R/ W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24WC01/02/04/08/16’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E = 255 for 24WC02, 511 for 24WC04, 1023 for 24WC08, and 2047 for 24WC16), then the counter will 'wrap around' to address 0 and continue to clock out data. If N = E (where E = 127 for the CAT24WC01) the counter will not 'wrap around'. BYTE ADDRESS SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24WC01/02/04/08/16 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24WC01/02/04/08/16 in a single write cycle. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24WC01/02/04/08/16 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24WC01/02/04/ 08/16 is still busy with the write operation, no ACK will be returned. If the CAT24WC01/02/04/08/16 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. |
同様の部品番号 - CAT24WC08WITE13F |
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同様の説明 - CAT24WC08WITE13F |
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