MC100LVEL92DWR2 datasheet(1/6 Pages) ONSEMI

部品番号	MC100LVEL92DWR2

部品情報	5V Triple PECL Input to LVPECL Output Translator

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November, 2006 − Rev. 11

1

Publication Order Number:

MC100LVEL92/D

MC100LVEL92

5VTriple PECL Input to

LVPECL Output Translator

Description

The MC100LVEL92 is a triple PECL input to LVPECL output

translator. The device receives standard PECL signals and translates

them to differential LVPECL output signals.

To accomplish the PECL to LVPECL level translation, the

MC100LVEL92 requires three power rails. The VCC supply is to be

connected to the standard 5 V PECL supply, the LVCC supply is to be

connected to the 3.3 V LVPECL supply, and Ground is connected to

the system ground plane. Both the VCC and LVCC should be bypassed

to ground with 0.01

mf capacitors.

The PECL VBB pin, an internally generated voltage supply, is

available to this device only. For single-ended input conditions, the

unused differential input is connected to VBB as a switching reference

voltage. VBB may also rebias AC coupled inputs. When used,

decouple VBB and VCC via a 0.01 mF capacitor and limit current

sourcing or sinking to 0.5 mA. When not used, VBB should be

left open.

Features

• 500 ps Propagation Delays

• 5 V and 3.3 V Supplies Required

• ESD Protection: Human Body Model; >2 kV,

Machine Model; >200 V

• The 100 Series Contains Temperature Compensation

• LVPECL Operating Range: LVCC = 3.0 V to 3.8 V

• PECL Operating Range: VCC = 4.5 V to 5.5 V

• Internal Input Pulldown Resistors

• Q Output will Default LOW with Inputs Open or < GND + 1.3 V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index 28 to 34

• Transistor Count = 247 devices

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

MARKING DIAGRAM*

A

= Assembly Location

WL

= Wafer Lot

YY

= Year

WW

= Work Week

G= Pb−Free Package

SO−20 WB

DW SUFFIX

CASE 751D

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

20

1

100LVEL92

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同様の部品番号 - MC100LVEL92DWR2

メーカー	部品番号	データシート	部品情報
ON Semiconductor	MC100LVEL92DWR2G	147Kb / 5P	5V Triple PECL Input to LVPECL Output Translator July, 2016 ??Rev. 13

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同様の説明 - MC100LVEL92DWR2

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