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MC10138 データシート(PDF) 4 Page - ON Semiconductor

部品番号 MC10138
部品情報  Bi-Quinary Counter
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10138 データシート(HTML) 4 Page - ON Semiconductor

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MC10138
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4
ELECTRICAL CHARACTERISTICS (continued)
NOTE: Each MECL 10,000 series circuit has
been designed to meet the dc specifications
TEST VOLTAGE VALUES (Volts)
been designed to meet the dc specifications
shown in the test table, after thermal
equilibrium has been established. The circuit
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
equilibrium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained Outputs are
–30
°C
–0.890
–1.890
–1.205
–1.500
–5.2
g
than 500 linear fpm is maintained. Outputs are
terminated through a 50–ohm resistor to –2.0
volts. Test procedures are shown for only one
+25
°C
–0.810
–1.850
–1.105
–1.475
–5.2
volts. Test procedures are shown for only one
gate. The other gates are tested in the same
manner.
+85
°C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
Pin
Under
Test
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
Power Supply Drain Current
IE
8
9
8
1, 16
Input Current
IinH
12
5,6,10,11
7
9
12
5,6,10,11
7
9
8
8
8
8
1, 16
1, 16
1, 16
1, 16
IinL
All
Note 1.
8
1, 16
Output Voltage
Logic 1
VOH
3,14 (3.)
2,4,13,15 (2.)
9
5,6,10,11
8
8
1, 16
1, 16
Output Voltage
Logic 0
VOL
3,14 (2.)
2,4,13,15 (3.)
5,6,10,11
9
8
8
1, 16
1, 16
Threshold Voltage
Logic 1
VOHA
2,4,13,15 (2.)
3,14 (3.)
13,15 (2.)
5,6,10,11
9
7,12
8
8
8
1, 16
1, 16
1, 16
Threshold Voltage
Logic 0
VOLA
2,4,13,15 (3.)
3,14 (2.)
13,15 (3.)
5,6,10,11
9
7,12
8
8
8
1, 16
1, 16
1, 16
Switching Times
(50
Ω Load)
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay Clock Delays
t12+15+
t12+14+
t7+13+
t7+4+
t7+2+
t7+3+
15
14
13
4
2
3
12
12
7
7
7
7
15
14
13
4
2
3
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
t12+15–
t12+14–
t7+13–
t7+4–
t7+2–
t7+3–
15
14
13
4
2
3
12
12
7
7
7
7
15
14
13
4
2
3
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
Set Delay
t11+15+
t11+14–
15
14
11
11
15
14
8
8
1, 16
1, 16
Reset Delay
t9+14+
t9+15–
14
15
9
9
14
15
8
8
1, 16
1, 16
Rise Time
(20 to 80%)
t14+
t15+
14
15
11
11
14
15
8
8
1, 16
1, 16
Fall Time
(20 to 80%)
t14–
t15–
14
15
9
9
14
15
8
8
1, 16
1, 16
Counting Frequency
fcount
2
15
7
12
2
15
8
8
1, 16
1, 16
1. Individually test each input; apply VILmin to pin under test.
2. Set all four flip–flops by applying pulse
VIHmax
VILmin
to pins 5, 6, 10, and 11 prior to applying test voltage indicated.
3. Reset all four flip–flops by applying pulse
VIHmax
VILmin
to pin 9 prior to applying test voltage indicated.


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