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CAT25C128LAT2 データシート(PDF) 8 Page - Catalyst Semiconductor |
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CAT25C128LAT2 データシート(HTML) 8 Page - Catalyst Semiconductor |
8 / 12 page ![]() CAT25C128/256 8 Document No. 1018, Rev. I properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address (the three Most Significant Bits are don’t care for 25C256 and four most significant bits are don't care for 25C128), and then the data to be written. Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illus- trated in Figure 4. Reading status register is illustrated in Figure 5. WRITE Sequence The CAT25C128/256 powers up in a Write Disable state. Prior to any write instructions, the WREN instruc- tion must be sent to CAT25C128/256. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C128/256. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been SK SI SO 0000001 1 BYTE ADDRESS* 0123456789 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 *Please check the instruction set table for address CS OPCODE DATA OUT MSB HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) — ——— Figure 4. Read Instruction Timing Figure 5. RDSR Timing 0 1 2 345 67 8 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 CS 00 0 00 1 0 1 Note: Dashed Line= mode (1, 1) — ——— |
同様の部品番号 - CAT25C128LAT2 |
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同様の説明 - CAT25C128LAT2 |
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