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74F161A データシート(PDF) 3 Page - Fairchild Semiconductor |
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74F161A データシート(HTML) 3 Page - Fairchild Semiconductor |
3 / 11 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74F161A, 74F163A Rev. 1.0.2 3 Functional Description The 74F161A and 74F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 74F161A) occur as a result of, and synchronous with, the LOW-to- HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of prece- dence: asynchronous reset (74F161A), synchronous reset (74F163A), parallel load, count-up and hold. Five control inputs—Master Reset (MR, 74F161A), Synchro- nous Reset (SR, 74F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)— determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel load- ing and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR ('F161A) or SR (74F163A) HIGH, CEP and CET permit counting when both are HIGH. Con- versely, a LOW signal on either CEP or CET inhibits counting. The 74F161A and 74F163A use D-type edge triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, pro- vided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. To implement syn- chronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 74F568 data sheet. The TC output is subject to decoding spikes due to internal race condi- tions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: 1. For 74F163A only State Diagram SR(1) PE CET CEP Action on the Rising Clock Edge ( ) L X X X Reset (Clear) HL XX Load (Pn→Qn) HH HH Count (Increment) HH LX No Change (Hold) HH XL No Change (Hold) |
同様の部品番号 - 74F161A_07 |
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同様の説明 - 74F161A_07 |
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