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ATMEGA1280 データシート(PDF) 34 Page - ATMEL Corporation

部品番号 ATMEGA1280
部品情報  8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
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メーカー  ATMEL [ATMEL Corporation]
ホームページ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA1280 データシート(HTML) 34 Page - ATMEL Corporation

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34
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation
is in progress, it is neither possible to read the EEPROM, nor to change the EEAR
Register.
General Purpose registers
GPIOR2 – General Purpose I/O
Register 2
GPIOR1 – General Purpose I/O
Register 1
GPIOR0 – General Purpose I/O
Register 0
External Memory registers
XMCRA – External Memory
Control Register A
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-
rides any pin direction settings in the respective data direction registers. Writing SRE to
zero, disables the External Memory Interface and the normal pin and data direction set-
tings are used.
• Bit 6:4 – SRL2:0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses.
The external memory address space can be divided in two sectors that have separate
wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table
7 and Figure 13. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the
entire external memory address space is treated as one sector. When the entire SRAM
Bit
7654
321
0
0x2B (0x4B)
MSB
LSB
GPIOR2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0000
000
0
Bit
7654
321
0
0x2A (0x4A)
MSB
LSB
GPIOR1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0000
000
0
Bit
7654
321
0
0x1E (0x3E)
MSB
LSB
GPIOR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0000
000
0
Bit
7654
321
0
“(0x74)”
SRE
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
XMCRA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0000
000
0


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