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ATTINY2313-20MU データシート(PDF) 75 Page - ATMEL Corporation |
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ATTINY2313-20MU データシート(HTML) 75 Page - ATMEL Corporation |
75 / 231 page 75 ATtiny2313/V 2543I–AVR–04/06 Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk T0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 34 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 34. Timer/Counter Timing Diagram, no Prescaling Figure 34 shows the same timing data, but with the prescaler enabled. Figure 35. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O/8) Figure 36 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 36. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk_I/O/8) clk Tn (clk I/O/1) TOVn clk I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) |
同様の部品番号 - ATTINY2313-20MU |
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同様の説明 - ATTINY2313-20MU |
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