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FAN5617 データシート(PDF) 8 Page - Fairchild Semiconductor |
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FAN5617 データシート(HTML) 8 Page - Fairchild Semiconductor |
8 / 10 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5617 Rev. 1.0.1 Circuit Description (Continued) IDLE T BIT LOGIC 1 LOGIC 0 BIT 0 BIT 1 BIT 4 T LOW T RESET IDLE T BIT STOP BIT DATA LATCHED T HIGH Figure 13. TinyWire™ Protocol Timing NBR data is shifted in LSB first on the DATA line, as shown in Figure 13. The TinyWire protocol operates over a wide range of TBIT times (see Table 3), allowing easy encoding of the brightness control bit-stream using a microcontroller software “bit-bang” loop. The 5-bit control word begins with the falling edge of DATA. If DATA is HIGH for a greater percentage of the time than it is low between falling edges, the bit is a “1.” If DATA is LOW longer than it is HIGH, the bit is a “0.” Observe the following timing rules to ensure proper data transmission: BIT = TLOW THIGH 0 > 75% TBIT < 25% TBIT 1 < 25% TBIT > 75 % TBIT Table 2. Data Bit Definition MIN. MAX. TLOW 500ns 40 μs THIGH 500ns 40 μs TRESET 100 μs Table 3. Timing Requirements Time BIT = TLOW THIGH TBIT MIN. 0 1500ns 500ns 2 μs MAX. 0 40 μs 13 μs 53 μs MIN. 1 500ns 1500ns 2 μs MAX. 1 13 μs 40 μs 53 μs Table 4. Minimum and Maximum Bit Times Each falling edge of DATA clocks in the value of its preceding bit, necessitating a STOP pulse of at least TLOW(MIN) width. The command word, NBR (see Table 1. NBR Data Dimming Values) , transfers to the internal registers and is valid at the rising edge of the STOP bit. A RESET is generated to the internal bit counters after the DATA line remains high for at least 100 μs. If less than five bits are received before the RESET occurs, no new data is transferred to the internal registers. If more than five bits are received before RESET, the first five bits are transferred at the rising edge of the sixth bit and subsequent bits are ignored. Short-Circuit and Thermal Protection In the event of an output voltage short circuit, the output current is limited to a typical value of 65mA. In addition, when the die temperature exceeds 150°C, a reset occurs and remains in effect until the die cools down to 135°C; at which time, the circuit restarts and resumes normal operation. Selecting Capacitors It is important to select the appropriate capacitor types and values for the FAN5617 circuit design. To reduce battery ripple, both CIN and COUT should be low-ESR capacitors. If necessary, the ripple can be further reduced by powering the IC through an RC input filter, as shown in Figure 14. FAN5617 VIN GND 0.5 Ω BATTERY 10 μ + – 4.7 μ Figure 14. Battery Ripple Reduction CAP1 and CAP2 should be MLCC capacitors of 0.1µF to 1µF for best efficiency in boost mode. For better ILED regulation, 1µF bucket capacitors are recommended, particularly when ILED > 25mA and the battery discharges below 3V. PCB Layout Considerations For best performance, a solid ground plane is recommended on the back side of the PCB. All capacitors should be placed as close to the IC as possible and connected with reasonably thick traces to minimize the ESL and ESR parasitics. |
同様の部品番号 - FAN5617 |
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同様の説明 - FAN5617 |
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