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FIN1218 データシート(PDF) 3 Page - Fairchild Semiconductor |
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FIN1218 データシート(HTML) 3 Page - Fairchild Semiconductor |
3 / 17 page 3 www.fairchildsemi.com Transmitters Pin Descriptions Connection Diagram FIN1217 and FIN1215 (21:3 Transmitter) Pin Assignment for TSSOP Pin Names I/O Type Number of Pins Description of Signals TxIn I 21 LVTTL Level Inputs TxCLKIn I 1 LVTTL Level Clock Input The rising edge is for data strobe. TxOut O 3 Positive LVDS Differential Data Output TxOut O 3 Negative LVDS Differential Data Output TxCLKOut O 1 Positive LVDS Differential Clock Output TxCLKOut O 1 Negative LVDS Differential Clock Output PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in high-impedance state. PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Outputs LVDS GND I 3 Ground Pins for LVDS Outputs VCC I 4 Power Supply Pins for LVTTL Inputs GND I 5 Ground pins for LVTTL Inputs NC No Connect |
同様の部品番号 - FIN1218 |
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同様の説明 - FIN1218 |
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