データシートサーチシステム |
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CD4051B データシート(PDF) 9 Page - Harris Corporation |
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CD4051B データシート(HTML) 9 Page - Harris Corporation |
9 / 15 page 9 Test Circuits and Waveforms FIGURE 9. TYPICAL BIAS VOLTAGES FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON (RL = 1kΩ) FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF (RL = 1kΩ) FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF VDD = 5V VSS = 0V VEE = -7.5V 7 8 (B) (C) (D) (A) VDD = 7.5V 7.5V 16 16 16 16 7 8 7 8 VDD = 5V VDD = 15V VSS = 0V VEE = 0V 7 8 5V VEE = -10V VSS = 0V VSS = 0V 5V VEE = -5V NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD. tf = 20ns 10% 10% 90% 50% 10% 50% 90% 10% 50% 90% tr = 20ns TURN-OFF TIME TURN-ON TIME tf = 20ns 10% 90% 50% 10% 50% 90% 10% 90% tr = 20ns TURN-OFF TIME TURN-ON tPHZ TIME VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IDD IDD IDD VDD VDD CD4053 CD4052 CD4051 CD4051B, CD4052B, CD4053B |
同様の部品番号 - CD4051B |
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同様の説明 - CD4051B |
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