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CS8405A-IZ データシート(PDF) 6 Page - Cirrus Logic |
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CS8405A-IZ データシート(HTML) 6 Page - Cirrus Logic |
6 / 37 page CS8405A 6 DS469F2 SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF) SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF) Notes: 6. The active edge of ISCLK is programmable. 7. The polarity of ILRCK is programmable. 8. No more than 128 SCLK per frame. 9. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed. 10. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 - - µs OMCK Frequency for OMCK = 512 * Fso 4.1 - 55.3 MHz OMCK Low and High Width for OMCK = 512 * Fso 7.2 - - ns OMCK Frequency for OMCK = 384 * Fso 3.1 - 41.5 MHz OMCK Low and High Width for OMCK = 384 * Fso 10.8 - - ns OMCK Frequency for OMCK = 256 * Fso 2.0 - 27.7 MHz OMCK Low and High Width for OMCK = 256 * Fso 14.4 - - ns Frame Rate 8.0 - 108.0 kHz AES3 Transmitter Output Jitter - - 1 ns Parameter Symbol Min Typ Max Units SDIN Setup Time Before ISCLK Active Edge (Note 6) tds 20 - - ns SDIN Hold Time After ISCLK Active Edge (Note 6) tdh 20 - - ns Master Mode OMCK to ISCLK active edge delay (Note 6) tsmd 0 - 10 ns OMCK to ILRCK delay (Note 7) tlmd 0 - 10 ns ISCLK and ILRCK Duty Cycle - 50 - % Slave Mode ISCLK Period (Note 8) tsckw 36 - - ns ISCLK Input Low Width tsckl 14 - - ns ISCLK Input High Width tsckh 14 - - ns ISCLK Active Edge to ILRCK Edge (Note 6,7,9) tlrckd 20 - - ns ILRCK Edge Setup Before ISCLK Active Edge (Note 6,7,10) tlrcks 20 - - ns |
同様の部品番号 - CS8405A-IZ |
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同様の説明 - CS8405A-IZ |
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