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AM29DL322D データシート(PDF) 11 Page - Advanced Micro Devices |
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AM29DL322D データシート(HTML) 11 Page - Advanced Micro Devices |
11 / 56 page 10 Am29DL322D/323D/324D December 13, 2005 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dr ess acc e ss t i mi ngs p r ov i de new da ta wh en addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to deter mine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex- ecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embed- ded Algorithms). The system can read data t RH after the RESET# pin returns to V IH. I CC4 in the DC Characteristics table represents the reset current. Also refer to AC Characteristics tables for RESET# timing parameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Device Bank Divisions Device Part Number Bank 1 Bank 2 Megabits Sector Sizes Megabits Sector Sizes Am29DL322D 4 Mbit Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword 28 Mbit Fifty-six 64 Kbyte/32 Kword Am29DL323D 8 Mbit Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword 24 Mbit Forty-eight 64 Kbyte/32 Kword Am29DL324D 16 Mbit Eight 8 Kbyte/4 Kword, thirty-one 64 Kbyte/32 Kword 16 Mbit Thirty-two 64 Kbyte/32 Kword |
同様の部品番号 - AM29DL322D_05 |
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同様の説明 - AM29DL322D_05 |
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