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AM29BL802CB-80RDGH1 データシート(PDF) 3 Page - SPANSION

部品番号. AM29BL802CB-80RDGH1
部品情報  8 Megabit (512 K x 16-Bit) CMOS 3.0 Volt-only, Burst-mode, Boot Sector Flash Memory-Die Revision 1
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AM29BL802CB-80RDGH1 Datasheet(HTML) 3 Page - SPANSION

 
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Am29BL802C Known Good Die
SU PP L E ME NT
GENERAL DESCRIPTION
The Am29BL802C in Known Good Die (KGD) form is
an 8 Mbit, 3.0 volt-only Flash memory. AMD defines
KGD as standard product in die form, tested for function-
ality and speed. AMD KGD products have the same reli-
ability and quality as AMD products in packaged form.
Am29BL802C Features
The Am29BL802C is an 8 Mbit, 3.0 Volt-only burst
mode Flash memory devices organized as 524, 288
words. These devices are designed to be programmed
in-system with the standard system 3.0-volt VCC
supply. A 12.0-volt VPP or 5.0 VCC is not required for
program or erase operations. The device can also be
programmed in standard EPROM programmers.
The device offers an access time of 80 ns, allowing
high speed microprocessors to operate without wait
states. To eliminate bus contention the device has sep-
arate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
Burst Mode Features
The Am29BL802C offers a Linear Burst mode—a
32 word sequential burst with wrap around—in a
bottom boot configuration only. This devices require
additional control pins for burst operations: Load
Burst Address (LBA#), Burst Address Advance
(BAA#), and Clock (CLK). This implementation allows
easy interface with minimal glue logic to a wide range
of microprocessors/microcontrollers for high perfor-
mance read operations.
AMD Flash Memory Features
Each device requires only a single 3.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. The I/O and control
signals are 5V tolerant.
The Am29BL802C is entirely command set compatible
with the JEDEC single-power-supply Flash stan-
dard. Commands are written to the command register
using standard microprocessor write timings. Register
contents serve as input to an internal state-machine
that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations dur-
ing power transitions. The hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Electrical Specifications
Refer to the Am29BL802C data sheet, publication
number 22371, for full electrical specifications on the
Am29BL802C in KGD form.


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