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AM29F002NBT-90PE データシート(PDF) 11 Page - Advanced Micro Devices |
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AM29F002NBT-90PE データシート(HTML) 11 Page - Advanced Micro Devices |
11 / 42 page November 1, 2006 21527D5 Am29F002B/Am29F002NB 9 D A TA SH EE T Status” for more information, and to each AC Charac- teristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins (CE# only on the Am29F002NB) are both held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins (CE# only on the Am29F002NB) are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification. RESET#: Hardware Reset Pin Note: The RESET# pin is not available on the Am29F002NB. The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the system drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state. Table 2. Am29F002B/Am29F002NB Top Boot Block Sector Address Table Sector A17 A16 A15 A14 A13 Sector Size (Kbytes) Address Range (in hexadecimal) SA0 0 0 X X X 64 00000h–0FFFFh SA1 0 1 X X X 64 10000h–1FFFFh SA2 1 0 X X X 64 20000h–2FFFFh SA3 1 1 0 X X 32 30000h–37FFFh SA4 1 1 1 0 0 8 38000h–39FFFh SA5 1 1 1 0 1 8 3A000h–3BFFFh SA6 1 1 1 1 X 16 3C000h–3FFFFh |
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同様の説明 - AM29F002NBT-90PE |
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