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AM29DL320GT50PCFN データシート(PDF) 5 Page - Advanced Micro Devices

部品番号 AM29DL320GT50PCFN
部品情報  32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29DL320GT50PCFN データシート(HTML) 5 Page - Advanced Micro Devices

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Am29DL320G
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TABLE OF CONTENTS
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Special Package Handling Instructions .......................................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Device Bus Operations .............................................................9
Word/Byte Configuration ................................................................ 9
Requirements for Reading Array Data ........................................... 9
Writing Commands/Command Sequences .................................. 10
Simultaneous Read/Write Operations
with Zero Latency ......................................................................... 10
Standby Mode .............................................................................. 10
Automatic Sleep Mode ................................................................. 10
RESET#: Hardware Reset Pin ..................................................... 11
Output Disable Mode ................................................................... 11
Table 2. Top Boot Sector Addresses ...................................................12
Table 3. Top Boot SecSi
TM Sector Addresses ..................................... 13
Table 4. Bottom Boot Sector Addresses ...............................................14
Table 5. Bottom Boot SecSi
TM Sector Addresses................................ 15
Autoselect Mode .......................................................................... 16
Table 6. Autoselect Codes, (High Voltage Method) .............................16
Sector/Sector Block Protection and Unprotection ........................ 17
Table 7. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................17
Table 8. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................17
Write Protect (WP#) ..................................................................... 18
Temporary Sector Unprotect ........................................................ 18
Figure 1. Temporary Sector Unprotect Operation................................. 18
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ............................................................ 19
SecSi
TM (Secured Silicon) Sector
Flash Memory Region .................................................................. 20
Figure 3. SecSi Sector Protect Verify.................................................... 21
Hardware Data Protection ............................................................ 21
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 9. CFI Query Identification String ................................................ 22
Table 10. System Interface String......................................................... 22
Table 11. Device Geometry Definition .................................................. 23
Table 12. Primary Vendor-Specific Extended Query ............................ 23
Reading Array Data ...................................................................... 24
Reset Command .......................................................................... 24
Autoselect Command Sequence .................................................. 24
Enter SecSi
TM Sector/Exit SecSi Sector
Command Sequence ................................................................... 25
Byte/Word Program Command Sequence ................................... 25
Figure 4. Program Operation ................................................................ 26
Chip Erase Command Sequence ................................................. 26
Sector Erase Command Sequence .............................................. 26
Erase Suspend/Erase Resume Commands ................................ 27
Figure 5. Erase Operation .................................................................... 27
Table 13. Command Definitions ........................................................... 28
DQ7: Data# Polling ...................................................................... 29
Figure 6. Data# Polling Algorithm ......................................................... 29
RY/BY#: Ready/Busy# ................................................................. 30
DQ6: Toggle Bit I .......................................................................... 30
Figure 7. Toggle Bit Algorithm .............................................................. 30
DQ2: Toggle Bit II ......................................................................... 31
Reading Toggle Bits DQ6/DQ2 .................................................... 31
DQ5: Exceeded Timing Limits ...................................................... 31
DQ3: Sector Erase Timer ............................................................. 31
Table 14. Write Operation Status ......................................................... 32
Figure 8. Maximum Negative Overshoot Waveform............................. 33
Figure 9. Maximum Positive Overshoot Waveform .............................. 33
Figure 10. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents).................................................................... 35
Figure 11. Typical I
CC1 vs. Frequency................................................... 35
Figure 12. Test Setup .......................................................................... 36
Figure 13. Input Waveforms and Measurement Levels ........................ 36
Figure 14. Read Operation Timings...................................................... 37
Figure 15. Reset Timings...................................................................... 38
Word/Byte Configuration (BYTE#) ............................................... 39
Figure 16. BYTE# Timings for Read Operations .................................. 39
Figure 17. BYTE# Timings for Write Operations .................................. 39
Erase and Program Operations ................................................... 40
Figure 18. Program Operation Timings ................................................ 41
Figure 19. Accelerated Program Timing Diagram ................................ 41
Figure 20. Chip/Sector Erase Operation Timings ................................. 42
Figure 21. Back-to-back Read/Write Cycle Timings ............................. 43
Figure 22. Data# Polling Timings (During Embedded Algorithms) ....... 43
Figure 23. Toggle Bit Timings (During Embedded Algorithms) ............ 44
Figure 24. DQ2 vs. DQ6 ....................................................................... 44
Temporary Sector Unprotect ........................................................ 45
Figure 25. Temporary Sector Unprotect Timing Diagram..................... 45
Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram 46
Alternate CE# Controlled Erase and Program Operations ........... 47
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49
TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm . 50
FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ......................... 51
TS 048—Thin Small Outline Package .......................................... 52


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