74ACT74SJ datasheet(6/10 Pages) FAIRCHILD

部品番号	74ACT74SJ

部品情報	Dual D-Type Positive Edge-Triggered Flip-Flop

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AC Operating Requirements for AC

Note 10: Voltage Range 3.3 is 3.3V

r 0.3V

Voltage Range 5.0 is 5.0V

r 0.5V

AC Electrical Characteristics for ACT

Note 11: Voltage Range 5.0 is 5.0V

r 0.5V

AC Operating Requirements for ACT

Note 12: Voltage Range 5.0 is 5.0V

r 0.5V

Capacitance

VCC

TA 25qCTA 40qC to 85qC

Symbol

Parameter

(V)

CL 50 pF

Units

(Note 10)

Typ

Guaranteed Minimum

tS

Set-up Time, HIGH or LOW

3.3

1.5

4.0

4.5

ns

Dn to CPn

5.0

1.0

3.0

tH

Hold Time, HIGH or LOW

3.3

2.0

0.5

ns

Dn to CPn

5.0

1.5

0.5

tW

CPn or CDn or SDn

3.3

3.0

5.5

7.0

ns

Pulse Width

5.0

2.5

4.5

5.0

trec

Recovery Time

3.3

2.5

0

ns

CDn or SDn to CP

5.0

2.0

0

VCC

TA 25qCTA 40qC to 85qC

Symbol

Parameter

(V)

CL 50 pF

Units

(Note 11)

Min

TypMax

MinMax

fMAX

Maximum Clock

5.0

145

210

125

MHz

Frequency

tPLH

Propagation Delay

5.0

3.0

5.5

9.5

2.5

10.5

ns

CDn or SDn to Qn or Qn

tPHL

Propagation Delay

5.0

3.0

6.0

10.0

3.0

11.5

ns

CDn or SDn to Qn or Qn

tPLH

Propagation Delay

5.0

4.0

7.5

11.0

4.0

13.0.

ns

CPn to Qn or Qn

tPHL

Propagation Delay

5.0

3.5

6.0

10.0

3.0

11.5

ns

CPn to Qn or Qn

VCC

TA 25qCTA 40qC to 85qC

Symbol

Parameter

(V)

CL 50 pF

Units

(Note 12)

Typ

Guaranteed Minimum

tS

Set-up Time, HIGH or LOW

5.0

1.0

3.0

3.5

ns

Dn to CPn

tH

Hold Time, HIGH or LOW

5.0

0.5

1.0

ns

Dn to CPn

tW

CPn or CDn or SDn

5.0

3.0

5.0

6.0

ns

Pulse Width

trec

Recovery Time

5.0

2.5

0

ns

CDn or SDn to CP

Symbol

Parameter

Typ

Units

Conditions

CIN

Input Capacitance

4.5

pF

VCC OPEN

CPD

Power Dissipation Capacitance

35.0

pF

VCC 5.0V

同様の部品番号 - 74ACT74SJ

メーカー	部品番号	データシート	部品情報
Fairchild Semiconductor	74ACT74SJ	104Kb / 9P	Dual D-Type Positive Edge-Triggered Flip-Flop

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