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データシートサーチシステム |
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74F269SC データシート(PDF) 6 Page - Fairchild Semiconductor |
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74F269SC データシート(HTML) 6 Page - Fairchild Semiconductor |
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6 / 9 page  ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74F269 Rev. 1.0.2 6 AC Electrical Characteristics AC Operating Requirements Symbol Parameter TA = +25°C, VCC = +5.0V, CL = 50pF TA = 0°C to 70°C, VCC = +5.0V, CL = 50pF Units Min. Typ. Max. Min. Max. fMAX Maximum Count Frequency 100 MHz tPLH Propagation Delay, CP to Qn (Count-Up) 3.5 8.0 3.5 7.0 ns tPHL 4.5 10.5 4.5 11.0 tPLH Propagation Delay, U/D to TC 3.5 7.5 3.5 10.0 ns tPHL 4.5 7.5 4.5 11.0 tPLH Propagation Delay, CET to TC 3.5 7.0 3.5 10.5 ns tPHL 3.0 10.5 3.0 11.5 tPLH Propagation Delay, CP to TC 4.5 10.0 4.5 10.5 ns tPHL 5.0 10.0 4.5 10.5 tPLH Propagation Delay, CP to Qn (Count-Down) 3.5 10.5 3.5 11.0 ns tPHL 4.5 10.5 4.5 11.0 tPLH Propagation Delay, CP to Qn (Load) 3.5 7.0 3.5 10.0 ns tPHL 4.0 7.0 4.0 7.0 Symbol Parameter TA = +25°C, VCC = +5.0V TA = 0°C to 70°C, VCC = +5.0V Units Min. Max. Min. Max. tS(H) Setup Time, HIGH or LOW, Data to CP 3.5 4.0 ns tS(L) 3.0 3.0 tH(H) Hold Time, HIGH or LOW, Data to CP 1.0 2.0 ns tH(L) 1.0 1.0 tS(H) Setup Time, HIGH or LOW, PE to CP 5.5 6.5 ns tS(L) 5.5 6.5 tH(H) Hold Time, HIGH or LOW, PE to CP 00 ns tH(L) 0 0 tS(H) Setup Time, HIGH or LOW, CET or CEP to CP 6.0 6.5 ns tS(L) 8.0 9.0 tH(H) Hold Time, HIGH or LOW, CET or CEP to CP 00 ns tH(L) 0 0 tW(H) Clock Pulse Width, HIGH or LOW 3.5 3.5 ns tW(L) 3.5 4.0 tS(H) Setup Time, HIGH or LOW, U/D to CP 8.0 9.5 ns tS(L) 6.0 7.0 tH(H) Hold Time, HIGH or LOW, U/D to CP 0.0 0.0 ns tH(L) 0.0 0.0 |
同様の部品番号 - 74F269SC |
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同様の説明 - 74F269SC |
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