データシートサーチシステム |
|
AM29F004BT-70JI データシート(PDF) 10 Page - SPANSION |
|
AM29F004BT-70JI データシート(HTML) 10 Page - SPANSION |
10 / 37 page 8 Am29F004B Am29F004B_00_E4 May 9, 2006 D A TA SH EE T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the com- mand. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29F004B Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 13 for more information. Refer to the AC Read Operations table for timing specifica- tions and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table repre- sents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the Command Definitions on page 13 section for details on erasing a sector or the entire chip, or sus- pending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode on page 10 and Autoselect Command Sequence sec- tions for more information. ICC2 in the DC Characteristics table represents the active curren t speci f i c a t ion fo r th e wri t e mode . The AC Characteristics on page 24 section contains timing specifica- tion tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7– DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 17 for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# pin is held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# pin is held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification. Operation CE# OE# WE# A0–A18 DQ0–DQ7 Read L L H AIN DOUT Write L H L AIN DIN CMOS Standby VCC ± 0.5 V X X X High-Z TTL Standby H X X X High-Z Output Disable L H H X High-Z Temporary Sector Unprotect (See Note) X X X X X |
同様の部品番号 - AM29F004BT-70JI |
|
同様の説明 - AM29F004BT-70JI |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |