データシートサーチシステム |
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DM74ALS646 データシート(PDF) 2 Page - Fairchild Semiconductor |
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DM74ALS646 データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Connection Diagram Function Table H = HIGH Logic Level L = LOW Logic Level X = Don’t Care (Either LOW or HIGH Logic Levels including transitions) H/L = Either LOW or HIGH Logic Level excluding transitions ↑ = Positive going edge of pulse Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Logic Diagram Inputs Data I/O (Note 1) Operation or Function G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8 XX ↑ X X X Input Not Specified Store A, B Unspecified XX X ↑ X X Not Specified Input Store B, A Unspecified HX ↑↑ X X Input Input Store A and B Data H X H/L H/L X X Input Input Isolation, Hold Storage L L X X X L Output Input Real-Time B Data to a Bus L L X H/L X H Output Input Stored B Data to a Bus L H X X L X Input Output Real-Time A Data to B Bus L H H/L X H X Input Output Stored A Data to B Bus |
同様の部品番号 - DM74ALS646_01 |
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同様の説明 - DM74ALS646_01 |
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