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FAN5236MTCX データシート(PDF) 3 Page - Fairchild Semiconductor

部品番号 FAN5236MTCX
部品情報  Dual Mobile-Friendly DDR / Dual-output PWM Controller
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN5236MTCX データシート(HTML) 3 Page - Fairchild Semiconductor

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FAN5236
PRODUCT SPECIFICATION
REV. 1.1.9 7/12/04
3
Pin Configurations
Pin Definitions
Pin
Number
Pin Name
Pin Function Description
1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
2
27
LDRV1
LDRV2
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
3
26
PGND1
PGND2
Power Ground. The return for the low-side MOSFET driver. Connect to source of low-
side MOSFET.
4
25
SW1
SW2
Switching node. Return for the high-side MOSFET driver and a current sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
5
24
HDRV1
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side
MOSFET.
6
23
BOOT1
BOOT2
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3.
7
22
ISNS1
ISNS2
Current Sense input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
8
21
EN1
EN2
Enable. Enables operation when pulled to logic high. Toggling EN will also reset the
regulator after a latched fault condition. These are CMOS inputs whose state is
indeterminate if left open.
9
20
FPWM1
FPWM2
Forced PWM mode. When logic low, inhibits the regulator from entering hysteretic mode.
Otherwise tie to VOUT. The regulator uses VOUT on this pin to ensure a smooth
transition from Hysteretic mode to PWM mode. When VOUT is expected to exceed VCC,
tie to VCC.
10
19
VSEN1
VSEN2
Output Voltage Sense. The feedback from the outputs. Used for regulation as well as
PG, under-voltage and over-voltage protection and monitoring.
11
ILIM1
Current Limit 1. A resistor from this pin to GND sets the current limit.
12
17
SS1
SS2
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter
during initialization. During initialization, this pin is charged with a 5
µA current source.
13
DDR
DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out
of phase.
AGND
LDRV1
PGND1
SW1
HDRV1
BOOT1
ISNS1
EN1
FPWM1
VSEN1
ILIM1
SS1
DDR
VIN
FAN5236
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
LDRV2
PGND2
SW2
HDRV2
BOOT2
ISNS2
EN2
FPWM2
VSEN2
ILIM2/REF2
SS2
PG2/REF2OUT
PG1
QSOP-28 or TSSOP-28
θ
JA
= 90
°C/W


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