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ISL12021CVZ データシート(PDF) 8 Page - Intersil Corporation

部品番号 ISL12021CVZ
部品情報  Real Time Clock with On Chip Temp Compensation 짹5ppm
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12021CVZ データシート(HTML) 8 Page - Intersil Corporation

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FN6451.0
March 30, 2007
Brown Out Detection
The ISL12021 monitors the VDD level continuously and
provides warning if the VDD level drops below the prescribed
levels. There are five (5) levels that could be selected for the
trip level. Typically set at the 85% of nominal VDD level. The
Real Time Clock Power Brown Out Bit ( LVDD) is set once
the VDD level drops below the trip point. The LVRST output
becomes active when the Power Brown Out Bit is set.
When the VDD power is re-established and is above the
85%VDD + 50mV trip point, the VPBM0 is set. The LVDD bit
is reset once it is read by the CPU. Note: The I2C comm link
remains active unless the Battery VTRIP levels are reached.
Battery Level Monitor
The ISL12021 has a built in warning feature once the Back
Up battery level drops first to 85% and then to 75% of the
battery’s nominal VBAT level. When the battery voltage
drops to between 85% and 75%, the LBAT85 bit is set in the
status register. When the level drops below 75%, both
LBAT85 and LBAT75 bits are set in the status register.
There is a Battery Timestamp Function available. Once the
VDD is low enough to enable switchover to the battery, the
RTC time/date are written into the TSVTB register. This
information can be read from the TSVTB registers to
discover the point in time of the VDD powerdown. If there are
multiple powerdown cycles before reading these registers,
the first values stored in these registers will be retained.
These registers will hold the original powerdown value until
they are cleared by writing “00h” to each register.
Low Power Mode
The normal power switching of the ISL12021 is designed to
switch into battery backup mode only if the VDD power is
lost. This will ensure that the device can accept a wide range
of backup voltages from many types of sources while reliably
switching into backup mode. Another mode (called Low
Power Mode) is available to allow direct switching from VDD
to VBAT without requiring VDD to drop below VTRIP. Since
the additional monitoring of VDD vs VTRIP is no longer
needed, that circuitry is shut down and less power is used
while operating from VDD. Power savings are typically
600nA at VDD = 5V. Low Power Mode is activated via the
BSW bit in the control and status registers.
Low Power Mode is useful in systems where VDD is normally
higher than VBAT at all times. The device will switch from
VDD to VBAT when VDD drops below VBAT, with about 50mV
of hysteresis to prevent any switchback of VDD after
switchover. In a system with VDD = 5V and backup lithium
battery of VBAT = 3V, Low Power Mode can be used.
However, it is not recommended to use Low Power Mode in
a system with VDD = 3.3V ±10%, VBAT ≥ 3.0V, and when
there is a finite I-R voltage drop in the VDD line.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the ISL12021
powers up after the loss of both VDD and VBAT, the clock will
not begin incrementing until at least one byte is written to the
clock register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing single
event or interrupt alarm mode is selected via the IM bit. Note
that when the frequency output function is enabled, the
alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ pin will be pulled low and the
alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ pin will be pulled low for 250ms and the alarm
status bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit). The
alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see “ALARM Registers (10h to 15h)” on
page 16.
Frequency Output Mode
The ISL12021 has the option to provide a clock output signal
using the FOUT open drain output pin. The frequency output
mode is set by using the FO bits to select 15 possible output
frequency values from 1/32Hz to 32kHz. The frequency
output can be enabled/disabled during battery backup mode
using the FOBATB bit.
General Purpose User SRAM
The ISL12021 provides 128 bytes of user SRAM. The SRAM
will continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
I2C Serial Interface
The ISL12021 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bi-directional data
signal (SDA) and a clock signal (SCL).
ISL12021


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