© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FM75 Rev. 1.0.8

9

Temperature Register

The temperature register is a two-byte (16-bit) read-only

register. Digital temperatures from the T-to-D converter

are stored in the temperature register in two’s comple-

ment format and the contents of this register are updated

at regular intervals, each time the T-to-D conversion is

finished.

The user can read data from the temperature register at

any time. When a T-to-D conversion is completed, the

new data is loaded into a comparator buffer to evaluate

fault conditions and updates the temperature register if a

read cycle is not ongoing. The FM75 is continuously

evaluating fault conditions regardless of read or write

activity on the bus. If a read is ongoing, the previous

temperature is read. The readable temperature is

updated upon the completion of the next T-to-D conver-

sion not masked by a read cycle.

The temperature register is illustrated in Figure 7.

Depending on the resolution of the T-to-D conversion,

the 9, 10, 11, or 12 MSBs of the register contain temper-

ature data. All unused bits following the digital tempera-

ture are zero. The MSB position of the temperature

register always contains the sign bit for the digital tem-

perature and bit 14 contains the temperature MSB. Bits

in the temperature register default to zero at power-up.

SB = Two’s complement sign bit

TMSB = Temperature MSB

T = Temperature data

9-bit LSB = Temperature LSB for 9-bit conversions

10-bit LSB = Temperature LSB for 10-bit conversions

11-bit LSB = Temperature LSB for 11-bit conversions

12-bit LSB = Temperature LSB for 12-bit conversions

Figure 7. Temperature Register Format

Configuration Register

The configuration register is a one-byte (8-bit) read/write

register (see Figure 8). This register allows the user to

control the FM75 shutdown mode as well as the follow-

ing thermal alarm features: polarity, operating mode, and

fault tolerance. The configuration register contains two

bits that set the fault tolerance trip point. The fault toler-

ance trip point is the number of consecutive times the

internal circuit reads the temperature and finds the tem-

perature outside the limits programmed. The pro-

Table 4 shows the relationship between F1 and F0 and

the number of consecutive errors or “trips” needed to

activate the alarm. The configuration register also con-

tains the two bits that set the T-to-D conversion resolu-

tion to 9, 10, 11, or 12 bits. Table 3 shows the

relationship between R1 and T0 and the conversion res-

olution. All bits in the configuration register default to

zero at power-up.

R1 = Resolution bit 1 (see Table 3).

R0 = Resolution bit 0 (see Table 3).

F1 = Fault tolerance bit 1 (see Table 4).

F0 = Fault tolerance bit 0 (see Table 4).

POL = OS output polarity: 0 = active low, 1 = active

high.

CMP/INT = thermostat mode: 0 = comparator mode,

1 = inerrupt mode.

SD = shutdown: 0 = normal operation, 1 = shutdown

mode.

Figure 8. Configuration Register Format

Table 3. Conversion Resolution Settings

Table 4. Fault Tolerance Settings

TTT

T

T

MSB

8

14

13

12

11

10

9

9-bit

LSB

00

0

0

7

LSB

6

5

4

3

2

1

10-bit

LSB

11-bit

LSB

12-bit

LSB

A-to-D

Conversion Resolution

R1

R0

9 Bits

0

0

10 Bits

0

1

11 Bits

1

0

12 Bits

1

1

Fault Tolerance

R1

R0

10

0

20

1

41

0

61

1

INT

SD

MSB

LSB

6

54

3

21