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SN74ABT8952DLR データシート(PDF) 9 Page - Texas Instruments |
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SN74ABT8952DLR データシート(HTML) 9 Page - Texas Instruments |
9 / 29 page SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS SCBS121D – AUGUST 1992 – REVISED JULY 1996 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 data register description boundary-scan register The boundary-scan register (BSR) is 38 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and two BSCs for each normal-function I/O pin (one for input data and one for output data). The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, the value of each BSC is reset to logic 0 except BSCs 37–36, which are reset to logic 1. The BSR order of scan is from TDI through bits 37–0 to TDO. Table 1 shows the BSR bits and their associated device pin signals. Table 1. Boundary-Scan Register Configuration BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL 37 OEAB 31 A8-I 23 A8-O 15 B8-I 7 B8-O 36 OEBA 30 A7-I 22 A7-O 14 B7-I 6 B7-O 35 CLKAB 29 A6-I 21 A6-O 13 B6-I 5 B6-O 34 CLKBA 28 A5-I 20 A5-O 12 B5-I 4 B5-O 33 CLKENAB 27 A4-I 19 A4-O 11 B4-I 3 B4-O 32 CLKENBA 26 A3-I 18 A3-O 10 B3-I 2 B3-O –– –– 25 A2-I 17 A2-O 9 B2-I 1 B2-O –– –– 24 A1-I 16 A1-O 8 B1-I 0 B1-O |
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