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SN74SSTU32864DZKER データシート(PDF) 2 Page - Texas Instruments |
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SN74SSTU32864DZKER データシート(HTML) 2 Page - Texas Instruments |
2 / 20 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or logic low level. The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR control and forces the output low. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. The two VREF pins (A3 and T3) are connected together internally by approximately 150 Ω. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor. 2 |
同様の部品番号 - SN74SSTU32864DZKER |
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同様の説明 - SN74SSTU32864DZKER |
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