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AD8117 データシート(PDF) 6 Page - Analog Devices |
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AD8117 データシート(HTML) 6 Page - Analog Devices |
6 / 36 page AD8117/AD8118 Rev. A | Page 6 of 36 TIMING CHARACTERISTICS (PARALLEL MODE) Specifications subject to change without notice. Table 4. Limit Parameter Symbol Min Typ Max Unit Parallel Data Setup Time t1 80 ns WE Pulse Width t2 110 ns Parallel Data Hold Time t3 150 ns WE Pulse Separation t4 90 ns WE to UPDATE Delay t5 10 ns UPDATE Pulse Width t6 90 ns Propagation Delay, UPDATE to Switch On or Off 100 ns RESET Pulse Width 60 ns RESET Time 200 ns t2 t4 1 0 WE 1 0 t1 t3 1 = LATCHED 0 = TRANSPARENT UPDATE t6 D0 TO D5 A0 TO A4 t5 Figure 3. Timing Diagram, Parallel Mode Table 5. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL RESET, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE RESET, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE DATA OUT DATA OUT RESET1, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE RESET1, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE DATA OUT DATA OUT 2.0 V min 0.6 V max Disabled Disabled 1 μA max –1 μA min Disabled Disabled 1 See Figure 15. |
同様の部品番号 - AD8117_07 |
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同様の説明 - AD8117_07 |
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