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TLV2474IPWPRG4 データシート(PDF) 18 Page - Texas Instruments

部品番号 TLV2474IPWPRG4
部品情報  FAMILY OF 600mA/Ch 2.8MHz RAIL-TO-RAIL INPUT/OUTPUT HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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TLV2474IPWPRG4 データシート(HTML) 18 Page - Texas Instruments

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DIE
Side View (a)
End View (b)
Bottom View (c)
DIE
Thermal
Pad
P
D
+
T
MAX
* TA
q
JA
(1)
TLV2470
,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
SLOS232D – JUNE 1999 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
The thermal pad is electrically isolated from all terminals in the package.
Figure 46. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
1. The thermal pad must be connected to the most negative supply voltage on the device (GND pin).
2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawing
at the end of this document. There should be etch for the leads as well as etch for the thermal pad.
3. Place holes in the area of the thermal pad as illustrated in the land pattern mechanical drawing at the end
of this document. These holes should be 13mils in diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane that is at the same voltage potential as the device GND pin.
6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes the soldering of vias that have plane connections
easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal
ground plane with a complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
9. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
For a given
θ
JA, the maximum power dissipation is shown in Figure 47 and is calculated by Equation 1:
Where:
• P
D = Maximum power dissipation of TLV247x IC (watts)
• T
MAX = Absolute maximum junction temperature (+150°C)
• T
A = Free-ambient air temperature (°C)
• θ
JA = θJC + θCA
θ
JC = Thermal coefficient from junction to case
θ
CA = Thermal coefficient from case to ambient air (°C/W)
18
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