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MC33977DW データシート(PDF) 7 Page - Freescale Semiconductor, Inc

部品番号 MC33977DW
部品情報  Single Gauge Driver
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC33977DW データシート(HTML) 7 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33977
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V
< VDD < 5.25 V, and -40°C < TA < 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT AND CLOCK TIMINGS (SIN+, SIN-, COS+, COS-) CS
SIN± (COS±) Output Turn ON Delay Time (Time from Rising CS
Enabling Outputs to Steady State Coil Voltages and Currents) (15)
tDLYON
1.0
ms
SIN± (COS±) Output Turn OFF Delay Time (Time from Rising CS
Disables Outputs to Steady State Coil Voltages and Currents) (15)
tDLYOFF
1.0
ms
Uncalibrated Oscillator Cycle Time
tCLU
0.65
1.0
1.7
µs
Calibrated Oscillator Cycle Time
Calibration Pulse = 8.0 µs, PECCR D4 = Logic [0]
Calibration Pulse = 8.0 µs, PECCR D4 = Logic [1]
tCLC
1.0
0.9
1.1
1.0
1.2
1.1
µs
Maximum Pointer Speed (16)
VMAX
400
°/s
Maximum Pointer Acceleration (16)
AMAX
4500
°/s2
SPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) (17)
Recommended Frequency of SPI Operation
fSPI
1.0
2.0
MHz
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (18)
tLEAD
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (18)
tLAG
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (18)
tSISU
25
83
ns
Falling Edge of SCLK to SI (Required Hold Time) (18)
tSIHOLD
25
83
ns
SO Rise Time
CL = 200 pF
tRSO
25
50
ns
SO Fall Time
CL = 200 pF
tFSO
25
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (19)
tRSI
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (19)
tFIS
50
ns
Falling Edge of RST to Rising Edge of RST (Required Setup Time) (18)
tWRST
3.0
µs
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (18), (20)
tCS
5.0
µs
Falling Edge of RST to Rising Edge of CS (Required Setup Time) (18)
tEN
5.0
µs
Notes
15.
Maximum specified time for the 33977 is the minimum guaranteed time needed from the microcontroller.
16.
The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.
17.
The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified
temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall
be fully functional for slower clock speeds. Reference Figure 4 and 5.
18.
The required setup times specified for the 33977 are the minimum time needed from the microcontroller to guarantee correct operation.
19.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
20.
The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.


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