データシートサーチシステム |
|
SA1638BE データシート(PDF) 8 Page - NXP Semiconductors |
|
SA1638BE データシート(HTML) 8 Page - NXP Semiconductors |
8 / 26 page Philips Semiconductors Product specification SA1638 Low voltage IF I/Q transceiver 1997 Sept 03 8 AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITS SYMBOL PARAMETER TEST CONDITIONS MIN –3 σ TYP +3 σ MAX UNITS IF Synthesizer (cont.) DI CP I CP Relative output current variation4 IREF =31.2µA 0.1 1.3 2.5 ±10 % ∆ICP_M Output current matching5 IREF =31.2µA, VCP = VCCCP/2 ±12 % |ICP_L| Output leakage current VCP = 0.3V to VCCCP-0.3V -0.02 0.1 0.22 ±15 nA tON Turn ON time POnPLL = HI, to full charge pump current 15 µs tOFF Turn OFF time6 POnPLL = LO, to ICCCP, ICCDIG <5% of operational supply current 15 µs Serial Interface7 fCLOCK Clock frequency 10 MHz tSU Set-up time: DATA to CLOCK, CLOCK to STROBE 30 ns tH Hold time: CLOCK to DATA 30 ns tW Pulse width: CLOCK 30 ns tW Pulse width: STROBE 30 ns NOTES: 1. Parameter measured relative to modulation sideband amplitude. 2. After programming the DC offset register for minimum offset. DCRES = 562k Ω. 3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for GSM–mode = 8 µs with filter bandwidth setting resistor = 36kΩ). 4. The relative output current variation is defined thus: DI OUT I OUT + 2 @ (I 2 * I1) |(I 2 ) I1)| ; with V1 = 0.3V, V2 = VCCCP – 0.3V (see Figure 3). 5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on. 6. As soon as PONPLL is set to LO, the phase detector is reset and no charge pumps pulses are generated. 7. Guaranteed by design. 8. NF = 20 log Eno 4kTR * VG where, Eno is the output noise voltage measured in a 1Hz bandwidth, R = 1200Ω, VG = gain in dB. 9. Minimium frequency is guaranteed by design. I2 I1 I2 I1 V1 V2 CURRENT VOLTAGE SR00526 Figure 3. Relative Output Current Variation FUNCTIONAL DESCRIPTION Serial Programming Input The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program the counter ratios, charge pump current, status- and DC-offset register, mode select and test register. The programming data is structured into two 21-bit words; each word includes 4 chip address bits and 1 subaddress bit. Figure 2 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the value of the subaddress bit the data is latched into different working registers. Table 3 shows the contents of each word. Default States Upon power up (VCCDIG is applied) a reset signal is generated, which sets all registers to a default state. The logic level at the STROBE pin should be low during power up to guarantee a proper reset. These default states are shown in Table 3. Reference Divider The reference divider can be programmed to four different division ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide by 13. Main Divider The external VCO signal, applied to the LOIN and LOINX inputs, is divided by two and then fed to the main divider (:N). The main divider is a programmable 9 bit divider, the minimum division ratio is |
同様の部品番号 - SA1638BE |
|
同様の説明 - SA1638BE |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |