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ST16C650AIJ44 データシート(PDF) 4 Page - Exar Corporation |
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ST16C650AIJ44 データシート(HTML) 4 Page - Exar Corporation |
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4 / 52 page  ST16C650A xr 2.90V TO 5.5V UART WITH 32-BYTE FIFO REV. 5.0.1 4 INT 33 30 O Interrupt Output (active high) This output becomes active whenever the transmitter, receiver, line and/or modem status register has an active condition. See interrupt section for more details. This interrupt output may be set to normal active high or active high open source (see MCR bit-5) to provide wire-OR capability by connecting a 1k to 10k ohms resistor between this pin and ground. AS# 28 24 I Address Strobe input (active low) In the Intel bus mode, the leading-edge transition of AS# latches the chip selects (CS0, CS1, CS2#) and the address lines A0, A1 and A2. This input is used when the address lines are not stable for the duration of a read or write operation. In devices with top mark date code of "I2 YYWW" and newer, the address bus is latched even if this input is not used. These devices feature a ’0 ns’ address hold time. See “AC Electrical Characteristics” . If not required, this input can be perma- nently tied to GND. TXRDY# 27 23 O UART Transmitter Ready (active low) The output provides the TX FIFO/THR status. See Table 2. If it is not used, leave it unconnected. RXRDY# 32 29 O UART Receiver Ready (active low) This output provides the RX FIFO/RHR status for receive channel A. See Table 2. If it is not used, leave it unconnected. PC Mode Interface Signals. Connect SEL pin to GND to select PC Mode. A3 A4 A5 A6 A7 A8 A9 25 12 14 15 16 21 1 20 6 9 10 11 17 37 I PC mode additional Address Lines In the PC mode, these are the additional address lines from the host address bus. They are inputs to the on-board chip select decode function for COM 1-4 and LPT ports. See Table 1 for details. The pins A4 and A9 have internal 100kΩ pull-up resistors. AEN# 28 24 I Address Enable input (active low) When AEN# transition to logic 0, it decodes and validates COM 1-4 ports address per S1, S2 and S3 inputs. S1 S2 S3 23 10 35 21 5 31 I Select 1 to 3 These are the standard PC COM 1-4 ports and IRQ selection inputs. See Table 1 and Table 3 for details. The S1 pin has an internal 100kΩ pull-up resistor. IRQA IRQB IRQC 33 32 27 30 29 23 O Interrupt Request A, B and C Outputs (active high, tri-state) These are the interrupt outputs associated with COM 1-4 to be connected to the host data bus. See interrupt section for details. The Interrupt Requests A, B or C functions as IRQx to the PC bus. IRQx is enabled by setting MCR bit-3 to logic 1 and the desired interrupt(s) in the interrupt enable register (IER). LPT1# 17 12 O Line Printer Port-1 Decode Logic Output (active low) This pin functions as the PC standard LPT-1 printer port address decode logic out- put, see Table 1. The baud rate generator clock output, BAUDOUT#, is internally connected to the RCLK input in the PC mode. NAME 44- PLCC PIN # 48- TQFP PIN # TYPE DESCRIPTION |
同様の部品番号 - ST16C650AIJ44 |
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同様の説明 - ST16C650AIJ44 |
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