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TDA4886A データシート(PDF) 8 Page - NXP Semiconductors |
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TDA4886A データシート(HTML) 8 Page - NXP Semiconductors |
8 / 52 page 1998 Dec 04 8 Philips Semiconductors Product specification 140 MHz video controller with I2C-bus TDA4886A 1. Control bit FPOL = 0 The cathode voltage (DC-coupled) is divided by a voltage divider and fed back to the IC. During the output clamping pulse it is compared with an adjustable feedback reference voltage with a range of approximately 5.77 to 4.05 V. Any difference will lead to a reference black level correction (control bit PEDST = 0) or pedestal black level correction (control bit PEDST = 1) by charging or discharging the integrated capacitor which stores the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.5 V. For correct operation it is necessary that there is enough headroom for ultra black signals (negative brightness setting, pedestal black level if control bit PEDST = 1). Any clipping with the video supply voltage at the cathode can disturb the signal rise/fall times or the black level stabilization. 2. Control bit FPOL = 1 For applications with AC-coupled cathodes the signal outputs are fed back internally. During the output clamping pulse they are compared with a feedback reference voltage of approximately 0.75, 1.0, 1.25 or 1.5 V (depending on the values of control bits BLH2 and BLH1). These values ensure a good adaptability to discrete and integrated post amplifiers as well. For black level restoration the DAC outputs (FB/R1, FB/R2 and FB/R3) with a range of approximately 5.77 to 4.05 V can be used. The use of pedestal blanking allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit because the pedestal black level is the most negative output signal. 7.6 Clamping and blanking pulses The pin CLI of TDA4886A can be directly connected to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses. The threshold for the input clamping pulse (typical 3 V) is higher than the threshold for the vertical blanking pulse (typical 1.4 V) but there must be no blanking during input clamping. Thus vertical blanking only is enabled if no input clamping is detected. For this reason the input clamping pulse must have rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and vice versa. The internal vertical blanking pulse will be delayed by typical 270 ns. During the vertical blanking pulse at pin CLI signal blanking, brightness blanking and with control bit PEDST = 1 pedestal blanking will be activated. Input clamping pulses during vertical blanking will not switch off blanking. For proper input clamping the input signals have to be at black level during the input clamping pulse. An input pulse at pin HFB (e.g. horizontal flyback pulse) will be scanned with two thresholds. If the input pulse exceeds the first one (typical 1.4 V) signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking will be activated. If the input pulse exceeds the second one (typical 3 V) additionally output clamping will be activated. The vertical blanking pulse can also be mixed with the horizontal flyback pulse at pin HFB. 7.7 On Screen Display (OSD) If the fast blanking input signal at pin FBL exceeds the threshold (typical 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 120% of the nominal colour signal (approximately 74% of the maximum colour signal). The amplitude can be controlled by OSD contrast (driven by the I2C-bus) with a range of 12 dB. The OSD signals are inserted at the same point as the contrast controlled input signals and will be treated with brightness and gain control like normal input signals. With control bit DISO = 1 the OSD signal insertion and fast blanking (pin FBL) are disabled. 7.8 Subcontrast adjustment, contrast modulation and beam current limiting The pin LIM is a linear contrast control pin which allows subcontrast setting, contrast modulation and beam current limiting. The maximum contrast is defined by the actual I2C-bus setting. Input signals at pin LIM act on video and OSD signals and do not affect the contrast bit resolution. To achieve brightness uniformity over the screen, scan dependent contrast modulation is possible. |
同様の部品番号 - TDA4886A |
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同様の説明 - TDA4886A |
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