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TDA8354Q データシート(PDF) 7 Page - NXP Semiconductors |
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TDA8354Q データシート(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 1998 Sep 03 7 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q THERMAL CHARACTERISTICS CHARACTERISTICS VP = 12 V; Vflb = 45 V; fi = 50 Hz; Ii(bias) = 330 µA; Tamb =25 °C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-c) thermal resistance from junction to case 4 K/W Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply VP operating supply voltage 7.5 12 18 V Vflb flyback supply voltage 2 × VP 45 68 V Iq(av) average quiescent supply current during scan − 10 15 mA Iq quiescent supply current no signal; no load − 60 80 mA IVflb(av) average flyback supply current during scan −− 10 mA Output stage A and B Vloss voltage loss from pin 10 to 9 and from pin 5 to 6 Io = 3.2 A (p-p); note 1 −− 6.0 V voltage loss from pin 4 to 5 and from pin 9 to 8 −− 4.8 V voltage loss from pin 10 to 9 and from pin 5 to 6 Io = 2.2 A (p-p); note 1 −− 4.2 V voltage loss from pin 4 to 5 and from pin 9 to 8 −− 3.4 V LE linearity error adjacent blocks Io = 3.2 A (p-p); note 2 − 0.5 2 % not adjacent blocks Io = 3.2 A (p-p); note 2 − 0.5 3 % Vo output voltage swing (flyback) Vo(A) − Vo(B) Ii(diff) = 0.3 mA; Io = 1.6 A − 46 − V V offset offset voltage across RM Ii(diff)=0 Ii(bias) = 500 µA −− 15 mV Ii(bias) = 100 µA −− 13 mV ∆V offset(T) offset voltage as function of temperature Ii(diff) =0 −− 40 µV/K Vo(A), Vo(B) DC output voltage Ii(diff) = 0; note 3 −− V Gv(ol) open-loop voltage gain V9to5/V3to5 notes 4 and 5 − 60 − dB V3to5/V2to5 voltage ratio V3to5/V2to5 note 4 − 0 − dB fres frequency response ( −3 dB) open loop − 1 − kHz Gi current gain (Io/Ii(diff)) − 8000 − V P 2 ------- |
同様の部品番号 - TDA8354Q |
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同様の説明 - TDA8354Q |
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