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TDA8376 データシート(PDF) 10 Page - NXP Semiconductors |
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TDA8376 データシート(HTML) 10 Page - NXP Semiconductors |
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10 / 44 page  1996 Jan 26 10 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A 7 FUNCTIONAL DESCRIPTION 7.1 Video switches The circuit has two CVBS inputs and a Super-Video Home System (S-VHS) input. The input can be chosen by the I2C-bus. The input selector also has a position in which CVBSEXT is processed, unless there is a signal on the S-VHS input. When the input selector is in this position it switches to the S-VHS input if the S-VHS detector detects sync pulses on the S-VHS luminance input. The S-VHS detector output can be read by the I2C-bus. When the S-VHS option is not used the luminance input can be used as a second input for external CVBS signals. The choice is made via the CVS bit (see Table 1). The video switch circuit has two outputs which can be programmed in a different way. The input signal for the decoder is also available on the TXT output. Therefore this signal can be used to drive the teletext decoder and the SECAM add-on decoder. The signal on the PIP output can be chosen independent of the TXT output. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. The circuit contains a video identification circuit which checks whether a video signal is available at the selected video input. This circuit is independent of the synchronization circuit. The information of this identification circuit can also be used to switch the phase-1 ( ϕ1) loop to a low gain when no signal is received so that a stable OSD display is obtained. The video identification circuit can be switched on and off via the I2C-bus. 7.2 Integrated video filters, peaking and black stretcher The circuit contains a chrominance bandpass and trap circuit. The chrominance trap filter in the luminance path is designed for a symmetrical step response behaviour. The filters are realized by gyrator circuits and they are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realized by gyrator circuits. During SECAM reception the centre frequency of the chrominance trap is set to a value of approximately 4.2 MHz to obtain a better suppression of the SECAM carrier frequencies. The peaking function is achieved by two luminance delay cells each with a delay of 165 ns. The resulting peaking frequency is 3 MHz. The peaking is asymmetrical so that the overshoots in the direction of ‘black’ are approximately two times higher than those in the direction of ‘white’. This provides a better picture impression than a symmetrical peaking. The circuit contains a coring circuit to prevent the noise content of the video signal being amplified by the peaking circuit. This coring circuit can be switched-off when required. It is possible to connect a Colour Transient Improvement (CTI) or Picture Signal Improvement (PSI) IC to the TDA8376. The luminance signal which has passed the filter and delay line circuit is available externally. The output signal of the transient improvement circuit must be applied to the luminance input circuit. When the CTI function is not required the two pins must be AC-coupled. The luminance signal below 50 IRE can be stretched in accordance with the difference between the peak black level and the blanking level of the back-porch of the video signal. The black level stretcher can be switched-off by connecting pin 2 to the positive supply line. 7.3 Synchronization circuit The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is only used to detect whether the line oscillator is synchronized and not for transmitter identification. The first Phase-Locked Loop (PLL) has a very high-statical steepness so that the phase of the picture is independent of the line frequency. To prevent the horizontal synchronization being disturbed by anti-copy signals such as Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The position of this pulse is asymmetrical and the width is approximately 22 µs. The horizontal output signal is generated by an oscillator which operates at twice the line frequency. Its frequency is divided-by-two to lock the first control loop to the incoming signal. The time-constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched on. |
同様の部品番号 - TDA8376 |
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同様の説明 - TDA8376 |
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