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TDA8785 データシート(PDF) 11 Page - NXP Semiconductors

部品番号 TDA8785
部品情報  8-bit high-speed analog-to-digital converter with gain and offset controls
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8785 データシート(HTML) 11 Page - NXP Semiconductors

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1997 Dec 18
11
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
with gain and offset controls
TDA8785
Notes
1. Vos is proportional to the amplifier gain. For instance, Vos at 20 dB is the one indicated at 0 dB multiplied by 10.
2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and
analog grounds is recommended.
3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; fclk = 30 MHz; no external
filtering on pin 6 (B).
4. The data set-up time (tSU; DAT) is the minimum period preceding the rising edge of the clock, that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (tHD; DAT) is the minimum period following the rising edge
of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.
5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling
shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour.
The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time tX.
Timing
ADC DIGITAL OUTPUTS (CL = 15 pF)
tds
sampling delay time
1.5
ns
th
output hold time
7
−−
ns
td
output delay time
−−
16
ns
DAC OUTPUTS (PINS VDACO(p) AND VDACO(n))
tSU; DAT
data set-up time
note 4
−0.3
−−
ns
tHD; DAT
data hold time
note 4
−−
2ns
tS
DAC setting time (10 to 90%)
RL = 150 Ω; CL =15pF
8
ns
RSA
residual setting accuracy
note 5; see Fig.8
0.1
2.5
%
3-STATE OUTPUT DELAY TIMES (see Fig.5)
tdZH
enable HIGH
15
20
ns
tdZL
enable LOW
15
20
ns
tdHZ
disable HIGH
13
20
ns
tdLZ
disable LOW
10
20
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT


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