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TDA9150 データシート(PDF) 11 Page - NXP Semiconductors |
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TDA9150 データシート(HTML) 11 Page - NXP Semiconductors |
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11 / 36 page  July 1994 11 Philips Semiconductors Preliminary specification Programmable deflection controller TDA9150B Vertical part (pins 6, 8, 10, 11 and 12) SYNCHRONIZATION PULSE The VA input (pin 12) is a TTL-compatible CMOS input. Pulses at this input have to fulfil the timing requirements as illustrated in Fig.6. For correct detection the minimum pulse width for both the HIGH and LOW period is 2 internal clock periods. For further requirements on minimum pulse width see also Section “De-interlace”. VERTICAL PLACE GENERATOR With control bit CPR a compress to 75% of the adjusted values is possible in all modes of operation. This control bit is used to display 16 : 9 standard pictures on 4 : 3 displays. No new adjustment of other corrections, such as corner and S-correction, is required. With control bit VPR a reduction of the current during clipping, wait and stop modes to 20% of the nominal value can be selected, which will reduce the dissipation in the vertical drive circuits. The vertical start-scan data (subaddress 02) determines the vertical placement in the total range of 64 × 432 clock periods in 63 steps. The maximum number of synchronized lines per scan is 910 with an equivalent field frequency of 17.2 or 34.4 Hz for fH = 15625 or 31250 Hz respectively. The minimum number of synchronized lines per scan is 200 with an equivalent field frequency of 78 or 156 Hz for fH = 15 625 or 31250 Hz respectively. If the VA pulse is not present, the number of lines per scan will increase to 910.2. If the LLC is not present the vertical blanking will start within 2 µs. Amplitude control is automatic, with a settling time of 1 to 2 new fields and an accuracy of either 16/12 or 48/12 lines depending on the value of the GBS bit. Differences in the number of lines per field, as can occur in TXT or in multi-head VTR, will not affect the amplitude setting providing the differences are less than the value selected with GBS. This is called amplitude control guardband. The difference sequence and the difference sequence length are not important. DE-INTERLACE With de-interlace on (DINT = logic 0), the VA pulse is sampled with LLC at a position supplied by control bit DIP (de-interlace phase). When DIP = logic 0 sampling takes place 42 clock pulses after the leading edge of HA (T = Tline × 42/432). When DIP = logic 1 sampling takes place 258 clock pulses after the leading edge of HA (T = Tline × 258/432). The distance between the two selectable sampling points is (Tline × (258 − 42)/432) which is exactly half a line, thus de-interlace is possible in two directions. The duration of the VA pulse must, therefore, be sufficient to enable the HA pulse to caught, in this event an active time of minimum of half a line (see Fig.13 which has an integration time of Tline × 1⁄4 for the VA pulse). With de-interlace off, the VA pulse is sampled with the system clock. The leading edge is detected and used as the vertical reset. Selection of the positive or negative leading edge is achieved by the control bit VAP. VERTICAL GEOMETRY PROCESSING The vertical geometry processing is DC-coupled and therefore independent of field frequency. The external resistive conversion (RCONV) at pin 8 sets the reference current for both the vertical and EW geometry processing. A useful range is 100 to 150 µA, the recommended value is 120 µA. VERTICAL OUTPUTS The vertical outputs VOUTA and VOUTB on pins 10 and 11 together form a differential current output. The vertical amplitude can be varied over the range 80 to 120% in 63 steps via the I2C-bus (subaddress 00). Vertical S-correction is also applied to these outputs and can be set from 0 to 16% by subaddress 01 with a 6-bit resolution. The vertical off-centre shift (OFCS) shifts the vertical deflection current zero crossing with respect to the EW parabola bottom. The control range is −1.5 to +1.5% ( ±1⁄8 × I8) in 7 steps set by the least significant nibble at subaddress 03. |
同様の部品番号 - TDA9150 |
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同様の説明 - TDA9150 |
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