データシートサーチシステム |
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CDCE925 データシート(PDF) 3 Page - Texas Instruments |
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CDCE925 データシート(HTML) 3 Page - Texas Instruments |
3 / 21 page www.ti.com EEPROM Xin/CLK Xout VDD GND InputClock Vctr S0 Programming and SDA/SCL Register Y2 Y1 Y3 LV CMOS Pdiv1 10-Bit LV CMOS Pdiv3 7-Bit Pdiv2 7-Bit PLL Bypass LV CMOS PLL 1 withSSC S1/SDA S2/SCL VCXO XO LVCMOS VDDOUT ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE (1) (2) CDCE913 CDCEL913 SCAS849A – JUNE 2007 – REVISED AUGUST 2007 over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VDD Supply voltage range –0.5 to 2.5 V VI Input voltage range(2) –0.5 to VDD + 0.5 V VO Output voltage range(2) –0.5 to VDD + 0.5 V II Input current (VI < 0, VI > VDD) 20 mA IO Continuous output current 50 mA Tstg Storage temperature range –65 to 150 °C TJ Maximum junction temperature 125 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. over operating free-air temperature range (unless otherwise noted) AIRFLOW TSSOP14 PARAMETER (lfm) °C/W 0 112 150 105 TJA Thermal resistance junction-to-ambient 250 102 500 97 TJC Thermal resistance junction-to-case – 46 (1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): CDCE913 CDCEL913 |
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同様の説明 - CDCE925 |
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