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AD7679ACPRL データシート(PDF) 7 Page - Analog Devices |
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AD7679ACPRL データシート(HTML) 7 Page - Analog Devices |
7 / 28 page AD7679 ABSOLUTE MAXIMUM RATINGS Table 5. AD7679 Absolute Maximum Ratings1 Parameter Rating Analog Inputs IN+2, IN–2, REF, REFBUFIN, REFGND to AGND AVDD + 0.3 V to AGND – 0.3 V Ground Voltage Differences AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD, OVDD –0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD –0.3 V to +7 V Digital Inputs –0.3 V to DVDD + 0.3 V Internal Power Dissipation3 700 mW Internal Power Dissipation4 2.5 W Junction Temperature 150°C Storage Temperature Range –65°C to +150°C Lead Temperature Range (Soldering 10 sec) 300°C 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2See An section. alog Inputs 3Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W. TO OUTPUT PIN CL 60pF1 500 µA IOH 1.6mA IOL 1.4V IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. 1 03085–0–002 Figure 2. Load Circuit for Digital Interface Timing SDOUT, SYNC, SCLK Outputs, CL = 10 pF 0.8V 2V 2V 0.8V t DELAY 2V 0.8V t DELAY 03085–0–003 Figure 3. Voltage Reference Levels for Timing Rev. 0 | Page 7 of 28 |
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