REV. 0

AD7843

–5–

PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Function

1, 10

be connected directly together.

2

X+

X+ Position Input. ADC Input Channel 1.

3

Y+

Y+ Position Input. ADC Input Channel 2.

4

X–

X– Position Input.

5

Y–

Y– Position Input.

6

GND

Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and

any external reference signal should be referred to this GND voltage.

7

IN3

Auxiliary Input 1. ADC Input Channel 3.

8

IN4

Auxiliary Input 2. ADC Input Channel 4.

Reference Input for the AD7843. An external reference must be applied to this input. The voltage

11

PENIRQ

Pen Interrupt. CMOS Logic open drain output (requires 10 k

Ω to 100 kΩ pull-up resistor externally).

12

DOUT

Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a

serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is

high impedance when

CS is high.

13

BUSY

BUSY Output. Logic Output. This output is high impedance when

CS is high.

14

DIN

Data In. Logic Input. Data to be written to the AD7843’s Control Register is provided on this input

and is clocked into the register on the rising edge of DCLK (see Control Register section).

15

CS

Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating con-

versions on the AD7843 and also enables the serial input/output register.

16

DCLK

External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part.

This clock input is also used as the clock source for the AD7843’s conversion process.

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1 LSB

below the first code transition, and full scale, a point 1 LSB

above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

error has been adjusted out.

Track/Hold Acquisition Time

The track/hold amplifier enters the acquisition phase on the fifth

falling edge of DCLK after the START bit has been detected.

Three DCLK cycles are allowed for the Track/Hold acquisition

time and the input signal will be fully acquired to the 12-bit

level within this time even with the maximum specified DCLK

frequency. See Analog Input section for more details.

On-Resistance

This is a measure of the ohmic resistance between the drain and

source of the switch drivers.