LMX2322

Advance Information

9/24/1998

Rev 1.6

9

2.2.1 10-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

R_CNTR

Divide

Ratio

9

8

7

6

5

4

3

2

1

0

2

0

0

0

0

0

0

0

0

1

0

3

0

0

0

0

0

0

0

0

1

1

•

•

•

•

•

•

•

•

•

•

•

1,023

1

1

1

1

1

1

1

1

1

1

NOTES: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited)

R_CNTR - These bits select the divide ratio of the programmable reference dividers

2.2.2 R Register Truth Table

BIT

LOCATION

FUNCTION

0

1

CP_TRI

R[11]

Charge Pump TRISTATE

Normal

operation

TRISTATE

PD_POL

R[12]

Phase Detector Polarity

Negative

Positive

TEST

R[14]

Test mode bit

Normal

operation

Test mode

If the test mode is NOT activated (R[14]=0), the charge pump is active when CP_TRI is set LOW. When

CP_TRI is set HIGH, the charge pump output and phase comparator are forced to a TRI-STATE condition. This

bit must be set HIGH if the test mode is ACTIVATED (R[14]=1).

If the test mode is NOT activated (R[14]=0), PD_POL sets the VCO characteristics to positive when set HIGH.

When PD_POL is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases

with increasing control voltage.

If the test mode is ACTIVATED (R[14]=1), the outputs of the N and R counters are directed to the CPo output to

allow for testing. The PD_POL bit selects which counter output according to Table 2.2.3.

2.2.3

Test mode truth table (R[14] = 1)

CPo Output

CP_TRI

R[11]

PD_POL

R[12]

R divider output

1

0

N divider output

1

1

2.3 N REGISTER

If the address bit is LOW (ADDR=0), when LE is transitioned high, data is transferred from the 18-bit shift register

into the 17-bit N register.

The N register consists of the 5-bit swallow counter (A counter), the 10 bit

programmable counter (B counter) and the control word. Serial data format is shown below in tables 2.3.1 and

2.3.2. The pulse swallow function which determines the divide ratio is described in section 2.3.3.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

NB_CNTR [9:0]

NA_CNTR[4:0]

CTL_WORD[1:0]

0