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SI533NC00100DGR データシート(PDF) 6 Page - Silicon Laboratories |
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SI533NC00100DGR データシート(HTML) 6 Page - Silicon Laboratories |
6 / 12 page Si533 6 Rev. 1.1 2. Pin Descriptions Pin # Symbol LVDS/LVPECL/CML Function CMOS Function 1OE* Output Enable* 0 = clock output disabled (outputs tristated) 1 = clock output enabled Output Enable* 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2FS* Frequency Select* 0 = First frequency selected 1 = Second frequency selected Frequency Select* 0 = First frequency selected 1 = Second frequency selected 3 GND Electrical and Case Ground Electrical and Case Ground 4 CLK+ Oscillator Output Oscillator Output 5 CLK– Complementary Output No Connection 6VDD Power Supply Voltage Power Supply Voltage *Note: FS and OE include a 17 k Ω pullup resistor to VDD. See Section 3. "Ordering Information" on page 7 for details on frequency value ordering. 1 2 3 6 5 4 GND FS VDD CLK+ CLK– OE (Top View) 1 2 3 6 5 4 GND FS VDD CLK NC OE LVDS/LVPECL/CML CMOS |
同様の部品番号 - SI533NC00100DGR |
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同様の説明 - SI533NC00100DGR |
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